In integrated circuit art, a commonly used method for forming interconnect structures that include metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer, which separates the vertically spaced metallization layers. The opening is typically formed using conventional photo lithography and etching techniques. After the formation, the opening is filled with copper or copper alloys. Excess copper on the surface of the dielectric layer is then removed by a Chemical Mechanical Polish (CMP) process. The remaining copper or copper alloy forms metal vias and/or metal lines.
The term damascene includes dual damascene and single damascene. In a dual damascene process, trenches and via openings are formed first. The via openings are substantially aligned to the conductive features such as metal lines in an underlying layer. The trenches and the via openings are then filled with a conductive material to form metal lines and vias, respectively. In a single damascene process, metal lines or vias, but not both, are formed at the same time.
The contact resistance values between vias and the underlying conductive features depend on the contact areas between the vias and the underlying conductive features. It is desirable that the contact resistance values are small so that the RC delay caused by the interconnect structure is low. However, misalignment may occur in the formation of via openings, and hence a via opening may have a portion not aligned with the underlying conductive feature. This results in contact resistance between the resulting via and the underlying conductive feature increasing undesirably.